One VEGA based SoC ASIC and two DIR V VEGA processor based development boards designed and developed by C-DAC were launched by Union Minister for Railways, Information & Broadcasting, Electronics & Information Technology Ashwini Vaishnaw, at C-DAC campus in Pashan, Pune today.
The two products, namely, ARIES ECO & ARIES NOVA development boards and THEJAS64 Indigenous 64-bit SoC are launched today. ARIES ECO is useful for students, providing a hands-on platform for experimenting with applications like sensor fusion, smart meters, and wearable devices. ARIES NOVA offers an easily accessible platform for education, research, and development in the rapidly evolving field of embedded systems. THEJAS64 is the first fully indigenous 64-bit VEGA based System-on-Chip (SoC) designed for robust and secure embedded applications.
As part of the Government of India’s Digital India RISC-V (DIR-V) program, C-DAC has successfully completed the design and development of the VEGA series of microprocessors including India’s first indigenous 64-bit multi-core RISC-V based Superscalar Out-of-order Processor. The VEGA series comprise of 32/64-bit Single/Dual/Quad Core superscalar Out-of-Order high performance processor cores based on RISC-V Instruction Set Architecture. The open-source RISC-V architecture enables flexibility and innovation and fosters hands-on learning and development in embedded systems.
Union Minister Ashwini Vaishnaw also visited an exhibition organized by C-DAC, followed by a review meeting with C-DAC scientists and officers. Speaking on the occasion, Union Minister Ashwini Vaishnaw said, computing and technological development is a core building block for India to become a developed country by 2047, and C-DAC plays a major role in it. Shri Vaishnaw said, a lot of research work in the field of semi-conductors and computing is happening in academic institutions like IIT Madras, IISc Bengaluru, IIT Gandhinagar among others. In the review meeting it was discussed as to how to bring together all research works together to create a consolidated and harmonized way of working going forward.
Vaishnaw said that around 240 institutions across the country today have very advanced tools which are used in designing semi conductor chips. C-DAC works as fulcrum of this entire programme by monitoring, enabling and purchasing licenses of these research tools.
As a result, students engaged with the research programmes, who used to earlier learn about semi-conductors only from textbooks, are now getting access to advanced tools, trying out their ideas and developing product concepts. Shri Vaishnaw further stated that these students who are working with semi conductor design tools are becoming ready to be absorbed in the semi-conductor industry, and also gather the inner strength to develop a start up and capability to actually design computer chips.
The Union Electronics and IT Minister Shri Vaishnaw also stated that C-DAC will run a challenge competition between students who have learned to use semi-conductor design tools, followed by connecting them with the best in the industry. C-DAC will also start a certification course for these students.
The Secretary of the Ministry of Electronics and Information Technology S. Krishnan, Group Co-ordinator (R&D), MeitY, Sunita Verma, Director General of C-DAC E Magesh and Centre Head of C-DAC Pune Sanjay Wandhekar along with and other senior officials were also present. C-DAC is the premier R&D organization of the MeitY, Government of India, to carry out R&D in IT, Electronics and associated areas.
